Database applications and database management systems typically use large amounts of memory. Maintaining application working sets in memory helps reduce storage I/O. In addition, data access patterns can cause large changes in the contents of the working set. These two factors make efficient memory management a determinant factor in database performance.
Memory management in virtual machines differs from physical machines in one key aspect: virtual memory address translation. Guest virtual memory addresses are translated to guest physical addresses using the guest operating system page tables. ESX then translates the guest physical addresses into machine physical addresses on the host. ESX maintains mappings from the guest virtual addresses to the machine physical addresses in shadow page tables. The shadow page tables allow ESX to avoid doing two levels of translation for every memory access and are cached in the hardware’s TLB. However, creating and maintaining the shadow page tables causes some overhead.
Hardware support for memory management unit virtualization is available in current processors. Offerings from Intel and AMD are called EPT and RVI, respectively. This support consists of an additional level of page tables implemented in hardware. These page tables contain guest physical to machine physical memory address translations.
While this hardware support obviates the need for maintaining shadow page tables (and the associated performance overhead) it introduces some costs of its own: TLB miss costs, in the form of increased latency, are higher because of the extra level of page tables. The number of TLB misses can be reduced by using large memory pages, a feature which has been available since ESX 3.5. Because TLB miss latency is higher with this hardware virtualization assist, use of large pages by the application in the virtual machine and availability of
large pages at the ESX level are a prerequisite for good database performance.
The following papers contain detailed descriptions of the hardware assist mechanisms and performance results from several benchmarks:
